Hi. I am trying to run a full-system multicore simulation using the ARM "VExpress_EMM" platform modeled in gem5. I am using the latest source codes from the gem5 repository.
I configured the system to have 4 processor cores and use the classic memory subsystem model, and created a checkpoint using a functional simulation assuming 4 cores with no caches. The checkpoint was created after the system was booted-up using functional simulation, and after I executed 4 different SPEC 2006 benchmarks. To exploit the checkpoint, I restored the checkpoint and then warmed-up the system using a TimingSimpleCPU. However, after the specified warm-up period, when I switch to O3CPU from TimingSimpleCPU, I get the following error. gem5.opt: build/ARM/python/swig/pyevent.cc:84: void cleanupCountedDrain(Event *): Assertion 'event->getCount()==0' failed Is there anyone who has faced the same issue as I described above? If so, how did you resolve the issue? Is multicore simulation stable in gem5 ARM architecture? Thanks. Best Regards, Kiyeon
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
