On Mon, 27 Aug 2012, Stijn Eyerman wrote:
Hi all,
Some time ago, I found out that it is not possible to simulate a core
supporting SMT in FS mode using gem5 (m5 at that time). Is this still the
case in the current version? If so, is this something that is taken care of?
This patch from Andrea Pellegrini supposedly fixes some problems with SMT
for x86 architecture, but it is yet to be checked in.
http://reviews.gem5.org/r/1281/
Certainly the mainline does not work correctly in SMT mode, and as far as
I know, no one is working on it.
And if not, can someone give a clue how to enable SMT in FS mode, and an
estimate how much work/time/experience this requires?
It might be that the above patch fixes everything that needs to be. I
suggest that you try out the patch and then raise any issues on the
mailing list.
Alternatively, has someone been able to run the PARSEC benchmarks in SE mode?
If so, how is OS scheduling modeled? Is there also something similar to
'quiesce' in FS mode (i.e., scheduling out threads)?
I think there are many users who are running PARSEC benchmarks in SE mode.
There is no scheduling in SE mode. My understanding is that you need at
least as many hardware contexts as the number of threads the application
creates.
--
Nilay
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