HI Korey, I had to make some InOrder specific experiments for microcode based ISAs for my research. So, I went through your detailed steps on the review board to implement microcode support for the InOrder CPU. However, I ran into a few issues:
1. The PreDecoder accepts a buffer in the form of MachInst to decode instructions. I assumed that it is the instruction itself (DynInst obtained from the ResourceRequest) in case of decode. When I tried using this to perform a pre-decode, I just got garbage. Am I missing something here? 2. I am currently using a loop to decode as many microOps as possible using the predecoder and put them in the sked buffer. However, I was wondering where do we quantify the amount of time spent during this operation? Thanks, Ashish On Mon, Jun 18, 2012 at 6:42 AM, Korey Sewell <[email protected]> wrote: > Hi Aziz/Erik, > Thanks for taking a look at the InOrder model w/ ARM. > > It seems you found a couple of compile issues that need to be > addressed for the InOrder model. However, I think I addressed those > issues in a patch to the reviewboard here: > http://reviews.m5sim.org/r/1013/ > > Secondly, like Erik said there is more to this issue then just getting > ARM to compile w/InOrder. The implementation of an ISA and CPU are two > different objects in gem5. While ARM is supported as an ISA in gem5, > the InOrder CPU model did not support timing translation and does not > support microcoding and thus cannot use ARM properly. > > The timing translation patch worked on heavily by Erik is here: > http://reviews.m5sim.org/r/1089/ > > Lastly, I recently posted the steps necessary to get microcoding in > InOrder in a separate patch here: > http://reviews.m5sim.org/r/1245/ > > My hope is that some motivated developer will take the reigns and I > could provide the "glue" support as this gets implemented. Of course, > its looking like that motivated developer will have to be me , but > that's ok....:) > > On Mon, Jun 18, 2012 at 6:17 AM, Erik Tomusk <[email protected]> wrote: >> Hi Aziz, >> >> Someone else might be able to give better advice, but the next thing you >> should do is probably take a step back. gem5 is complicated enough that >> blindly hacking in files won't fix anything. >> >> To compile the ARM in-order model into gem5, you need this patch: >> http://reviews.gem5.org/r/1013/ The in-order model will still fail during >> execution, but you can compile it in and start experimenting with the code. >> >> There are three things missing from the ARM in-order model: 1.) hardware >> table walking, 2.) predicated execution, and 3.) micro-coding. The patch >> here: http://reviews.gem5.org/r/1089/ tries to address #1. It compiles, but >> since #2 and #3 don't yet exist, it's impossible to test. >> >> Predicated execution is part of the ARM ISA, so that has to be there for a >> simulation to work. >> >> gem5 implements the ARMv7 ISA. There are some ARMv7 processors out there >> that aren't micro-coded, but I don't know whether that means it's possible >> for gem5 to simulate ARM without micro-coding. See this patch >> http://reviews.gem5.org/r/1245/ for an idea on what is needed for >> micro-coding. >> >> In short, I don't think it's possible to get the in-order model working >> without implementing the missing bits, but if you have time to implement >> some of them, it would be great. >> >> You should probably also take a look at the gem5 wiki and read up on the >> directory structure. Everything in gem5/build is created from gem5/src >> during building, so it doesn't make sense to copy something from gem5/build >> back into gem5/src. >> >> Hope this helps, >> Erik >> >> >> On 16/06/12 00:05, Aziz Eker wrote: >> >> Hello, >> >> I searched about in-order model for ARM. I looked at the status matrix in >> the documentation and according to that, in-order model "definitely does not >> work" with ARM. Then checking the mailing lists, in gem5-dev list I found >> Korey's email saying that the model is missing micro-code support. But, >> since I am not interested in micro-code support -for now- I attempted using >> it, i.e. I changed build_opts/ARM file to include InOrderCPU model and tried >> to build the simulator using scons getting the following error: >> >> [ CXX] ARM/arch/arm/generated/inorder_cpu_exec.cc -> .o >> In file included from build/ARM/cpu/inorder/inorder_dyn_inst.hh:41:0, >> from build/ARM/arch/arm/generated/inorder_cpu_exec.cc:9: >> build/ARM/arch/mt.hh:1:26: fatal error: arch/arm/mt.hh: No such file or >> directory >> compilation terminated. >> scons: *** [build/ARM/arch/arm/generated/inorder_cpu_exec.o] Error 1 >> scons: building terminated because of errors. >> >> Then I searched for mt.hh file and found under: >> ./src/arch/alpha/mt.hh >> ./src/arch/mips/mt.hh >> ./src/arch/sparc/mt.hh >> ./build/ARM/arch/mt.hh >> >> And copied ./build/ARM/arch/mt.hh to ./src/arch/arm/. But it gave more >> errors. >> Does anyone have an idea on what to do next? >> >> Thanks, >> Aziz >> >> >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> The University of Edinburgh is a charitable body, registered in >> Scotland, with registration number SC005336. >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > -- > - Korey > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
