Hi Yingying, It's likely that there is a bug in the protocol (because the wiki indicates that it is indeed inclusion). You will probably have to debug a bit. Try using the 'ProtocolTrace' debug flag to see the state transitions leading up to that print out.
Malek On Wed, Oct 17, 2012 at 1:44 AM, Cookie <cookie.yingy...@gmail.com> wrote: > Hi Malek, > > Thank you for your explanation. I still have a question. As you said, > > [NetDest (4) 0 1 - 0 0 - 0 - 0 - ] > In this case the tag is present only in the second L1Cache (L1Cache1) > > Why the tag is only in L1cache? Based on the MESI protocol (inclusive cache > hierarchy), a block in L1 cache should also be in the L2. Is it correct? > Thanks for your help. > > > Best, > Yingying > > > > Date: Tue, 16 Oct 2012 18:09:16 -0400 > From: Malek Musleh <malek.mus...@gmail.com> > To: gem5 users mailing list <gem5-users@gem5.org> > Subject: Re: [gem5-users] Questions about DataBlock in Ruby > Message-ID: > <capoxfjwy7zdhtz0d67hdm2hbrfxrymxyzoi+uhwhyggmbqw...@mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > > Hi Yingying, > > NetDest indicates in which of the Memory Caches the address is present > in the protocols MachineType. In the case for MESI there are 4: > (L1Cache, L2Cache, Directory, DMA). > > [NetDest (4) 0 1 - 0 0 - 0 - 0 - ] > > In this case the tag is present only in the second L1Cache (L1Cache1) > > [NetDest (4) 0 0 0 0 - 1 0 - 0 - 0 - ] > > In this case the tag is present only in the first L2Cache (L2Cache0) > > The << routine for NetDest prints the set in the order of L1Caches - > L2Cache - Directory - DMA. > > In both your simulations, you did not change the number of directories > or DMA Caches. > > Malek > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
