Thanks Nilay As you mentioned, I have gone through src/sim & mem/protocol files. Understood how Classes & Cache is maintained but still has few questions. It will be much helpful if get specific answers 1. If a var is shared between two processors, How data flow happens & how to trace the same in simulation? 2. How L1_TBEs is maintained ?
3. I am introducing a level of cache between L1 & L2 - For that I have to define a new cache in mem/protocol <newCache>.sm & update L1 & L2 transitions or is there some other way to do the same. Warm Regards Mann On Sat, Oct 6, 2012 at 5:29 PM, Nilay Vaish <[email protected]> wrote: > On Fri, 5 Oct 2012, Mann Mann wrote: > > Hi All >> in Shared Multiprocessor Simulation, I understood that simulator assigns >> sequencer to each process, but I need to grab exact flow, >> I want to understand how shared variables are used, and how data flow >> between these processors. >> (In detail : How virtual/physical page mapping is maintained in simulator) >> Could somebody suggest, where to look for this info. >> >> > Lots of documentation is available on gem5.org. That is good place to > start. Look in the directory src/sim. The files system.cc and process.cc > might be relevant to you. You can look at how the memory system works in > src/mem directory. > > -- > Nilay >
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
