No not yet, It has yet to be reviewed. Note the comment about 'misses' versus 'accesses'.
Malek On Wed, Oct 31, 2012 at 10:17 AM, Pavlos Maniotis <[email protected]> wrote: > Thank you Malek, I'll check this out. > > One more question: > Is this patch included in the latest development release? > > Thanks again, > > Pavlos > > On Wed, 2012-10-31 at 10:06 -0400, Malek Musleh wrote: >> Hi Pavlos, >> >> I have posted a patch on the review board that does this for >> MOESI/MESI Protocols. >> >> Take a look here: http://reviews.gem5.org/r/1467/ >> >> Malek >> >> On Tue, Oct 30, 2012 at 12:22 PM, Pavlos Maniotis <[email protected]> >> wrote: >> > Hello everyone, >> > >> > Could somebody please help me on how to calculate the >> > miss rate for L1 cache? >> > >> > I think I should divide "system.l1_cntrl0.cacheMemory_total_misses" >> > with total accesses to L1 to get the miss rate. >> > >> > What events do I have to sum to get the total accesses? >> > Should I sum all L1 events (example bellow) to get L1 >> > total accesses or some of them? >> > >> > Thanks in advance, >> > >> > Pavlos >> > >> > >> > An example of stats file is: >> > ------------------------------------------------------------------------ >> > Cache Stats: system.l1_cntrl0.cacheMemory >> > system.l1_cntrl0.cacheMemory_total_misses: 5612533 >> > system.l1_cntrl0.cacheMemory_total_demand_misses: 5612533 >> > system.l1_cntrl0.cacheMemory_total_prefetches: 0 >> > system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 >> > system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 >> > >> > system.l1_cntrl0.cacheMemory_request_type_LD: 58.6287% >> > system.l1_cntrl0.cacheMemory_request_type_ST: 9.00016% >> > system.l1_cntrl0.cacheMemory_request_type_ATOMIC: 0.805768% >> > system.l1_cntrl0.cacheMemory_request_type_IFETCH: 31.5654% >> > >> > system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 5612533 >> > 100% >> > >> > --- L1Cache --- >> > - Event Counts - >> > Load [16806362 ] 16806362 >> > Ifetch [97852127 ] 97852127 >> > Store [9267729 ] 9267729 >> > Data [5612533 ] 5612533 >> > Fwd_GETX [0 ] 0 >> > Inv [188 ] 188 >> > Replacement [5611927 ] 5611927 >> > Writeback_Ack [5612021 ] 5612021 >> > Writeback_Nack [0 ] 0 >> > ------------------------------------------------------------------------ >> > >> > _______________________________________________ >> > gem5-users mailing list >> > [email protected] >> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
