Hello All, I am trying to integrate the dramsim2 patch released recently by Tao Zhang located @http://www.mail-archive.com/[email protected]/msg05088.html (also attached) with gem5 for 'fs' mode (patch is integrated and tested for 'se' mode). I made changes in FSConfig.py file to set the 'physmem' to DRAMSim2 memory. Following is the change that I had to make to integrate DRAMSim2. -======================================================================================
# self.physmem = SimpleMemory(range =
# AddrRange(self.realview.mem_start_addr,
# size = mdesc.mem()),
# conf_table_reported = True)
self.physmem = DRAMSim2(
*range =
AddrRange(self.realview.mem_start_addr,size=mdesc.mem())*,
cpu_clock="2GHz",
deviceConfigFile =
os.path.join("/home/DREXEL/rb639/PowerAgileComputing/gem5/ext/DRAMSim2/ini/DDR3_micron_16M_8B_x8_sg15.ini"),
systemConfigFile=os.path.join("/home/DREXEL/rb639/PowerAgileComputing/gem5/ext/DRAMSim2/system.ini.example"),
)
-======================================================================================
Once I make this change, following is the error log:
-======================================================================================
warn: This is an integrated DRAMsim v2 module
Listening for system connection on port 5900
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
fatal: Expected a single ATAG memory entry but got 0
@ cycle 0
[initState:build/ARM/arch/arm/linux/system.cc, line 133]
Memory Usage: 557548 KBytes
-======================================================================================
To overcome the above error, I tried giving specific start addr in
'AddrRange', I replaced
range = AddrRange(*self.realview.mem_start_addr*,size=mdesc.mem()),
with the following
range = AddrRange(*Addr(mdesc.mem())*,size=mdesc.mem()),
or
range = AddrRange(*Addr('1MB')*,size=mdesc.mem()),
I end up with the below error :
======================================================================================
warn: This is an integrated DRAMsim v2 module
Listening for system connection on port 5900
Listening for system connection on port 3456
fatal: system.membus has two ports with same range:
system.physmem.port
system.bridge.slave
@ cycle 0
[recvRangeChange:build/ARM/mem/bus.cc, line 407]
Memory Usage: 554844 KBytes
======================================================================================
We are not sure, how to resolve the above error.
FYI, We have a working version (revision 8868) of gem5 integrated with
DRAMSim2 (released by Xiangyu Dong). However, we are trying to use the
latest version(revision 9197) of Gem5. The code snippet from the working
code is below
======================================================================================
# self.physmem = PhysicalMemory(range =
AddrRange(Addr(m5.options.memsize)),
# zero = True)
self.physmem = DRAMMemory(range =
AddrRange(Addr(m5.options.memsize)),
zero = True, log_file =
os.path.join(m5.options.outdir, "gem5dramsim2"),
memory_spec =
os.path.join("/archgroup/projects/poweragile/tools/gem5/ext/dramsim2/ini/DDR3_micron_32M_8B_x8_sg15.ini"),
mem_clock =
m5.options.memclock)#ini/DDR2_micron_32M_8B_x4_sg25E.ini"))
======================================================================================
Code looks much similar; however DRAMsim2 wrapper interface, and gem5 to
memory interface seem to have changed.
Any guidance regarding the above will be very helpful.
Thank you
-Rizwana
DRAMSim2_gem5_patch.tar.gz
Description: GNU Zip compressed data
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