Hello,
I was trying to figure out the MESI_CMP_directory cache coherence protocol in
gem5. From what I understand the directory system is based on a point to point
interconnection network -- does that mean that there is not a bus at all to
communicate on between caches/memory?
For example, if Cache 1 requests address 0x8 and the directory knows Cache 2
has modified this address, does Cache 1 have to wait for it to be written back
to main memory on a point to point connection from Cache 2 and then get the
address from main memory again on a point to point connection? Or is there some
bus/optimization where Cache 1 can just snoop the data from Cache 2 as it's
being written back to main memory?
I suppose I'm really just looking for better implementation details; what I've
found here (http://gem5.org/Cache_Coherence_Protocols#MESI_CMP_directory)
doesn't seem to mention a bus at all.
Thanks for any insight!
Jordan
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