absolutely right. Another way is:
-------------12bits for Tag-------------------4bits to select
bank----------8bits for index----------6 bits for block offset
your way maps contiguous blocks across different banks of a cache, so this is
really helpful if processor is reading contiguous data from memory pages.
Mine approach first put all contiguous blocks in one bank then next one and so
on....so may not provide good performance if data is contiguous.
________________________________
From: Nitin Chaturvedi <ntnb...@gmail.com>
To: gem5 users mailing list <gem5-users@gem5.org>
Sent: Saturday, 24 November 2012, 11:23
Subject: Re: [gem5-users] (no subject)
Dear sir
srry for wrong interpretation..........please check again and correct me if i
am wrong...........
my understanding.................
If......physical address space ........1GB.................size of physical
address 30-bits.......
Now,
1. if size of on chip L2 cache is 4MB
2. block size.........64byte
3. 16 banks and 16 way set associative
then physical address interpretation will be as follows
-------------12bits for Tag--------------------8bits for
index-----------------------4bits to select bank----------------------6 bits
for block offset
sir, please correct me if i am wrong.................. thanks
On Sat, Nov 24, 2012 at 11:28 AM, megha gupta <megha122...@gmail.com> wrote:
my understanding...................physical address space .........means on
chip L2 cache
>1. if size of on chip L2 cache is 4MB
>2. block size.........64byte
>3. 16 banks and 16 way set associative
>
>then physical address is of 50 bits and its interpretation will be as follows
>
>-------------32bits for Tag--------------------8bits for
>index-----------------------4bits to select bank----------------------6 bits
>for block offset
>
>
>sir, please correct me if i am wrong..................
--
Nitin Chaturvedi
Lecturer, EEE/IU
BITS, Pilani (Raj)
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