It's cycle approximate On 24 Nov 2012, at 09:32, Frank Yang wrote:
> Hi All, > > I am trying to dig into Gem5 but I found it's fairly complicated. Can someone > give me any hint on how gem5 bring the concept of timing into those CPU > models? I can understand that each instruction is divided into several > stages, but how is the magic gem5 does to fetch the instruction in each > cycle? And how to pass those intermediate value of each instruction generated > to the next cycle? I am still in the world of Verilog/VHDL, so it's hard for > me to figure this out in C++. Thanks for any of your input. > > -Yang > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
