If you are really wanting to change the "main memory", then have a look at SimpleMemory. Currently it only has a single latency parameter, but it wouldn't take too much effort to add a read/write latency.
Andreas From: Rodrigo Reynolds Ram�rez <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Thursday, 13 December 2012 15:37 To: gem5-users <[email protected]<mailto:[email protected]>> Subject: [gem5-users] Main memory different latencies Hello everyone: I am working with new memory's technologies. I need to simulate different read and write latencies. I see the simulator only has a "hitlatency". Is it possible to add different latencies for read and write accesses? I know "writes" are not in the critical path, but, is it possible to consider them in the statics? for example, in my case, writes are 200x slower than reads, if the write queue is full the system should stall until the L3 to main memory can be done, it could reduce the system performance Thanks in advance, Rodrigo -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
