HI Jordan, The protocol files themselves specified latencies for the different ports, rather than pulling them from the config files. For example in the MESI_CMP_directory-L1cache.sm file:
int l2_select_num_bits, int l1_request_latency = 2, int l1_response_latency = 2, int to_l2_latency = 1, these variables are used to indicate the latency of a protocol message when it is enqueued to a port. Thus, each port for the same cache could have different access latencies. Malek On Fri, Dec 21, 2012 at 5:14 PM, Jordan Fix <[email protected]> wrote: > Hello, > > I'm doing simulations with the Ruby memory system. I found a comment in > configs/ruby/MESI_CMP_directory.py that says: > > "# Note: the L2 Cache latency is not currently used" > > Does this mean that the ruby memory system for MESI_CMP_directory is not > timing accurate when going to the L2? What about latency when going to main > memory? > > Thanks. > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
