I have forgot to reference big tsunami PAL code. I am able to run it now.
I am trying to implement L3 cache using the same 2 level coherence protocol
by adding L3 between L2 and mem using toL3bus. How should I implement
connectAllPorts().
I have done it as
if options.l3cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.tol3bus)
system.cpu[i].connectAllPorts(system.tol3bus, system.membus)
elif options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
But it is not the right way to connect, because here I have l3bus as both
cached and uncached port. How should I connect all buses then.
Thanks,
PS: I am getting fatal error in this way
fatal: Port <orphan LinuxAlphaSystem>.cpu0.icache.mem_side is already
connected to <orphan LinuxAlphaSystem>.tol2bus.slave[0], cannot connect
<orphan LinuxAlphaSystem>.tol3bus.slave[1]
On Mon, Jan 28, 2013 at 7:21 PM, SHARAN MORA (RIT Student)
<[email protected]>wrote:
> Hi,
> I am trying to run ALPHA in full system mode with 8 processors. When I
> run, I get
>
> warn: clear IPI for CPU=0, but NO IPI
> warn: clear IPI for CPU=0, but NO IPI
> .
> .
>
> After some time I get
>
> warn: clear IPI for CPU=0, but NO IPI
> warn: clear IPI for CPU=1, but NO IPI
> .
> .
>
> How long will it take to run till checkpoint.
>
> Thanks,
>
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