Hello,
I would like to add more ports in my CPU in order to connect it with more than
one caches.
So in the /src/cpu/BaseCpu.py I changed these lines:
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
to
icache_port = MasterPort("Instruction Port")
dcache_port = MasterPort("Data Port")
second_icache_port = MasterPort("Instruction Port")
second_dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port',
'dcache_port','second_icache_port','second_dcache_port']
Now I will do the same in the BaseCache.py file where the cpu_sides are defined.
Am I right so far?
Do I need to duplicate the mem_side port as well?
And finally, in the function AddPrivateL1Caches where the connection takes
place is it enough to simply add these lines:
self.second_icache_port = ic.second_cpu_side
self.second_dcache_port = dc.second_cpu_side
Is there anything that I am missing?
Thanks,
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