Hello,
I have in my system 2 cpus with separate L1 D and I caches. Each of these
caches has two ports (cpu_side and second_cpu_side) because I want to connect
with both of the cpus.
So I am having these:
Cpu has:
dcache_port, second_dcache_port, icache_port, second_icache_port
and cache has:
cpu_side, second_cpu_side and mem_side.
I have made the appropriate changes in the .py and .hh,.cc files.
So I am calling this:
system.cpu.addPrivateSplitL1Caches(icache, dcache, newicache, newdcache)
and then this:
system.secondcpu.addPrivateSplitL1Caches(newicache, newdcache, icache, dcache)
and my addPrivateSplitL1Caches def is this:
def addPrivateSplitL1Caches(self, ic, dc, second_ic=None, second_dc=None,iwc =
None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
#code added by IGN - 17 Apr
self.second_icache = second_ic
self.second_dcache = second_dc
self.second_icache_port = second_ic.second_cpu_side
self.second_dcache_port = second_dc.second_cpu_side
#end of code
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
But the problem is that in my config I see:
[system.secondcpu.second_dcache], [system.secondcpu.second_icache] ,
[system.secondcpu.dcache] or [system.secondcpu.icache] twice
and i do not see at all:
[system.cpu.second_dcache] or [system.cpu.second_dcache] or [system.cpu.dcache]
or [system.cpu.dcache]
Any idea on why that might happen?
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