Hi Andreas,
For your first question, even though I agree that the modeling of queuing delay and memory scheduling are critical to the performance, a precise timing model is mandatory to capture an accurate (at least reasonable) performance result. All arbitration/prioritization of memory requests in the memory controller should abide with the rule that it has no timing violation (bank conflict and data bus conflict). As a result, it does not matter where the timing model is realized (either in memory controller or memory module) but the timing model should be precise. For the current SimpleDDR3, I am sure it is close to a precise model since the assumption of 3-tRP tRAS and 4-tRP tRC almost match the data sheet from Micron. For the second question, that's what I want to do some research work but stuck at no open source for the DDR controller. So currently it is hard to compare a memory controller model to a real ASIC. As result, I am also wondering whether the memory controller model is too powerful to be implemented in the silicon. -Tao From: [email protected] [mailto:[email protected]] On Behalf Of Andreas Hansson Sent: Thursday, May 09, 2013 6:00 AM To: gem5 users mailing list Subject: Re: [gem5-users] SimpleDRAM accuracy Hi Amin, Tao, My short answer is in fact a question rather than an answer: What accuracy are you referring to? The long answer: The SimpleDRAM model is capturing the behaviour of the memory controller rather than the DRAM itself (although the latter of course affects the former). Thus, the accuracy that the model aims to deliver is with respect to the behaviour as seen from the system. Certain DRAM parameters are indeed left out at the moment, and you could argue that this affects the precision of the modelling, but I would suggest the link to accuracy is not so clear. Having a more precise model of the DRAM does not necessarily give a more accurate model of the impact on the system. Accuracy vs precision :-). More important than a precise DRAM model is the queuing and arbitration of the controller. The low-power states are indeed important to model, especially from a power point of view, and this would be a great addition to the model. Another important question is: what do you want it to be accurate with respect to? If accuracy means correlation with real silicon, then what SoC/platform? To the best of my knowledge, neither the SimpleDRAM model, nor DRAMSim1/2 has been compared to an actual memory controller implementation (only the DRAM side of things for the latter). Such a comparison would also be of value. I hope that provides you with all the information you need in terms of making a choice. Other benefits of the SimpleDRAM models (DDR3, LPDDR2 etc) is that they are fast and very configurable. Andreas From: Tao Zhang <[email protected]> Reply-To: gem5 users mailing list <[email protected]> Date: Thursday, 9 May 2013 04:17 To: 'gem5 users mailing list' <[email protected]> Subject: Re: [gem5-users] SimpleDRAM accuracy Hi Amin, You can refer to Andreas's clarification for the similar concern. <http://www.mail-archive.com/[email protected]/msg07444.html> http://www.mail-archive.com/[email protected]/msg07444.html. As he said, you can use SimpleDDR3 or LPDDR2_S4 to capture a more accurate memory timing behavior. Compared to the simplest memory model that only assigns constant (average) latency to each memory request, the SimpleDRAM indeed has "good-enough accuracy". If you are working on the main memory part, then the good starting point is SimpleDDR3 rather than SimpleDRAM as the former has even better accuracy. In my case, I didn't compare SimpleDRAM or SimpleDDR3 with DRAMSim2. Since SimpleDDR3 has no timing parameter like tWR and tRRD, nor low power mode (tPD, tXP.), it has some performance difference from the real case. Again, you should decide whether the accuracy is good enough for your work. On the other hand, we really compared our own simulator NVMain ( <http://www.nvmain.org> http://www.nvmain.org ) with DRAMSim2. We got similar performance as the validation of our tool. If you are interested, you can ask for the source code on the website. -Tao From: [email protected] [mailto:[email protected]] On Behalf Of Amin Farmahini Sent: Wednesday, May 08, 2013 9:21 PM To: gem5 users mailing list Subject: [gem5-users] SimpleDRAM accuracy Hi, Comparing SimpleDRAM model and DRAMSim2 model, I was wondering how timing accurate SimpleDRAM is for memory-intensive applications? This might be a question for Andreas and Tao and I know this is a very general question, but any thoughts on this would be appreciated. Andreas mentioned that SimpleDRAM provides "good-enough accuracy." More information on the accuracy would be great. I realized some detailed parameters such as FAW are integrated into SimpleDRAM, and some other like RRD are left out. So my next question is whether there are any plans to model more detailed DRAM behavior? Thanks, Amin -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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