Hello again,
I moved forward a little bit from my previous question and the things are more
weird right now. I have made some changes in the gem5 and I have these:
For example for some read requests in the data cache:
3789000: system.secondmainCpu.dcache: ReadReq b8cf8 hit
3789000: system.secondmainCpu.dcache: pkt->needsExclusive(): false
3789000: system.secondmainCpu.dcache: blk->isWritable(): false
3789000: system.secondmainCpu.dcache: blk->isReadable(): false
3789000: system.secondmainCpu.dcache: cache_impl.hh, incMissCount for b8cf8,
called
3789000: system.secondmainCpu.dcache: ::timingAccess in cache_impl.hh. We have
a miss
So although it is a hit, because the block is not readable() the code deals
with it as a miss and not only the stats are
increased like it is a miss but also the actions for a miss are performed.
Similarly, in a WriteReq the block needs to be Writable and needExclusive(),
but the isWritable is false and it agains
considered as a miss.
So my question is where the block is inserted in the cache because something is
not set up correctly ?
Where the isWritable() or isReadable() are being set ?
Thanks,
Ignatios
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
