Hi, Ali,
Thanks for reply. From wiki I learn that X86 has a mode "X86-64", in which
the code size is 64 bits.
And from the generated code
_srcRegIdx[_numSrcRegs++] = (condCode == COND_AL || condCode == COND_UC
||
condCode == COND_CC || condCode == COND_CS ||
condCode == COND_VS || condCode == COND_VC) ?
INTREG_ZERO : INTREG_CONDCODES_NZ;
_srcRegIdx[_numSrcRegs++] = INTREG_CONDCODES_C;
_destRegIdx[_numDestRegs++] = INTREG_CONDCODES_C;
_numIntDestRegs++;
_srcRegIdx[_numSrcRegs++] = (condCode == COND_VS || condCode == COND_VC
||
condCode == COND_GE || condCode == COND_LT ||
condCode == COND_GT || condCode == COND_LE) ?
INTREG_CONDCODES_V : INTREG_ZERO;
I believe this is what you mean the "zero register" and the condition flags
works. From above code we can see the source regs include other things
besides the real source regs.
Thanks very much
Xiangyang
On Tue, Jul 2, 2013 at 2:15 PM, Ali Saidi <[email protected]> wrote:
> **
>
> 33 is likely the zero register (a special register that always returns 0,
> and is always ready). In cases where certain flags aren't required, the
> easiest way to communicate this information is to change the register
> values to the zero register instead of defining instructions with/without
> dependencies.
>
>
>
> Ali
>
>
>
> On 01.07.2013 16:29, Xiangyang Guo wrote:
>
> Hi, Ali,
>
> About the number of source register in one inst, I have another question:
> I print out the source registers by printing out "RegIndex src_reg =
> inst->srcRegIdx(src_idx);" , for example: in one inst, num of source regs
> is 4, but 3 registers among the 4 source registers are "33", and another 1
> register is "2". And it seems that the register "33" show up for many
> times in different inst.
>
> So if the register "33" is "things other than the explicit source
> registers", why it account for 3 times in one instruction? Thanks very much.
>
> regards
>
> Xiangyang
>
>
>
> On Mon, Jul 1, 2013 at 12:37 AM, Ali Saidi <[email protected]> wrote:
>
>> There are things other than the explicit source registers that need to be
>> accounted for (for example flag registers).
>>
>> Ali
>>
>> On Jun 30, 2013, at 3:08 PM, Xiangyang Guo <[email protected]> wrote:
>>
>> > Hi, Deal all,
>> >
>> > I use SE mode, ARM ISA and O3 cpu. I print out the num_src_regs,
>> "unsigned num_src_regs = inst->numSrcRegs(); " (src/cpu/o3/rename_impl.hh)
>> in the function DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,
>> ThreadID tid), and I find an intertesting thing: the number of source regs
>> are something like 3 or 4 or 5 or 6. Then I use X86 ISA and do the same
>> thing, and the source regs are even something like 8.
>> >
>> > So I think maybe I misunderstand something, because I think the num of
>> source regs in one inst should be smaller. so could anyone explain this?
>> Thanks in advance. In addition, just want to confirm, form my
>> understanding, the renamed inst is micro inst?
>> >
>> > Regards
>> >
>> > Xiangyang
>> > _______________________________________________
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