Hi, I have a question about O3CPU pipeline in GEM5. My understanding about the GEM5 O3CPU is that rename stage does not put instructions into instruction queue(issue queue) and ROB. Dispatch stage actually does the above. So, rename + dispatch in GEM5 is actually the rename stage of O3CPU. Please correct me if I am wrong. As the dispatch stage pushes the instructions into ROB and instruction Queue, I think that the free entries of ROB and instruction queue should be checked at this stage. However, the rename stage in gem5 check the free ROB and instruction queue size. I cannot understand this. Can anyone help explain?
Thanks! Zhiguo _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
