Hi,
I need to realize an separate L2 Instruction Cache and Data Cache using
classic memory mode in gem5. I guess that it may be related to
CacheConfig.py, and I did some modification of that file, but it didn't
work. The modified script is as follows.
def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2
else:
dcache_class, icache_class, l2i_class, l2d_class = \
L1Cache, L1Cache, L2Cache, L2Cache
## dcache_class, icache_class, l2_cache_class = \
## L1Cache, L1Cache, L2Cache
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2i = l2i_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc,
block_size=options.cacheline_size)
system.l2d = l2d_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc,
block_size=options.cacheline_size)
##system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
## size=options.l2_size,
## assoc=options.l2_assoc,
## block_size=options.cacheline_size)
system.tol2ibus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l2i.cpu_side = system.tol2ibus.master
system.l2i.mem_side = system.membus.slave
system.tol2dbus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l2d.cpu_side = system.tol2dbus.master
system.l2d.mem_side = system.membus.slave
##system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
## width = 32)
##system.l2.cpu_side = system.tol2bus.master
##system.l2.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc,
block_size=options.cacheline_size)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc,
block_size=options.cacheline_size)
# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
system.cpu[i].createInterruptController()
##if options.l2cache:
## system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
if options.l2cache:
system.cpu[i].icache.mem_side = system.tol2ibus.slave
system.cpu[i].dcache.mem_side = system.tol2dbus.slave
# system.cpu[i].itb_walker.port = system.tol2dbus.slave
# system.cpu[i].dtb_walker.port = system.tol2dbus.slave
system.cpu[i].connectUncachedPorts(system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
Can anybody tell me what to do? It would be just a single core, separate L1
I&D Cache, and separate L2 I&D Cache and Main memory.
Best regards
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