Hi All, I am simulating a 3 CPU system in FS mode, where I use slightly modified versions of arm_detailed for first two cpus and a timing model for the third cpu. I rewrote the cache_config function to get split private L1s and L1 TLBs and unified private L2 and L2 TLB for core0 and unified private L1, L1TLB and L2, L2 TLB for core1. core2 has no cache. All the remaining mem_side ports connect to system.membus. So this seems to be working, except on OS boot, I get the following error right around the time that core 1 is booting:
gem5.opt: build/ARM/mem/request.hh:471: uint64_t Request::getExtraData() const: Assertion `privateFlags.isSet(VALID_EXTRA_DATA)' failed. Program aborted at cycle 177650636400 I have fixed a lot of bugs before getting to this point, but this one seems to be really hard to debug on my own, so I'd appreciate any and all help I can get! Thanks a lot in advance, Tayyar _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
