Probably something you will need to fix if you change the cache line size
away from 64 bytes, would be great if you could post back the patch to fix
the issue.

Thanks,
Jack

Jack Harvard


On Fri, Apr 25, 2014 at 8:06 PM, Chetan Patil <chtpa...@gmail.com> wrote:

> Hi,
>
> I am trying to simulate X86 with varying cache line size. Following are
> the arguments I pass for Full System Mode simulation:
>
> build/X86/gem5.opt configs/example/fs.py --num-cpus=8 --caches
> --l1d_size=16kB --l1i_size=16kB --num-l2caches=1 --l2cache --l2_size=1MB
> --cacheline_size=64 --kernel=<PATH TO KERNEL> --disk-image=<PATH TO DISK
> IMAGE>
>
> I am using PARSEC X86 images.
>
> The simulation arguments work only if I keep cache line size to 64 bytes
> (which is the default size too). If I vary it to from: 16, 32, 128 and 256
> bytes then the simulation doesn't work and terminates either by throwing an
> error or by aborting.
>
> *1) Error with 16 & 32 cacheline size:*
>
> gem5.opt: build/X86/mem/cache/cache_impl.hh:147: void
> Cache<TagStore>::satisfyCpuSideRequest(Packet*, typename
> TagStore::BlkType*, bool, bool) [with TagStore = LRU]: Assertion
> `pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed.
>
> *2) Error with 128 & 256 cacheline size:*
>
> warn: Block size is neither 16, 32, 64 or 128 bytes.
> fatal: Slave port size 256, master port size 64                    (For
> 128 this line changes to: fatal: Slave port size 128, master port size 64)
>  Busses don't have the same block size... Not supported.
>  @ cycle 0
> [init:build/X86/mem/bridge.cc, line 116]
> Memory Usage: 805888 KBytes
>
> To resolve the issue, even modifying configs/common/Caches.py doesn't
> work. I have seen earlier post where modifying Caches.py resolved the
> issue. That isn't the case with me. Could anyone please point out the issue
> regarding master-slave port size and why the simulation terminates for
> small cache line size? Also, whether this is a bug or not?
>
> Thanks,
> Chetan Patil
>
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>
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