Hi Naveed, Are you using the latest gem5 trunk?
I was the one who changed Bus to XBar, so there was not much finding out to do. Good point though, I should update the Wiki. Andreas On 01/10/2014 06:05, "Naveed Ul Mustafa" <naveed.must...@bilkent.edu.tr> wrote: >Hi Anderson, > >Thanks for the reply, however I still face the problem. > >Following is the new script. >------------------------------------------ >#import m5 >#from m5.objects import * > > >import m5 >from m5.objects import * > >MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1, >response_latency=2) > >MyL1Cache=MyCache(is_top_level= True) > >mycpu = TimingSimpleCPU(cpu_id=0) > >mycpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), > MyL1Cache(size = '256kB'), > MyCache(size = '2MB', hit_latency=2, > response_latency=4)#Level2 Cache > ) > >mysystem = System( > cpu=mycpu, > cache_line_size = '64', > physmem = SimpleMemory(), > membus = CoherentXBar() > ) > ># Create a source clock for the system and set the clock period >mysystem.clk_domain = SrcClockDomain(clock='1GHz') > > >root = Root(full_system=False,system = mysystem) >root.system.cpu.workload=LiveProcess(cmd= 'hello', executable >='/home/naveed/Desktop/gem5/tests/test-progs/hello/bin/arm/linux') > ># instantiate configuration >m5.instantiate() > >#exit_event = m5.simulate() >print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() >--------------------------------------------------------- > >and I get the following error > >gem5 Simulator System. http://gem5.org >gem5 is copyrighted software; use the --copyright option for details. > >gem5 compiled Aug 28 2014 12:59:22 >gem5 started Oct 1 2014 08:00:23 >gem5 executing on naveed-desktop >command line: build/ARM/gem5.opt configs/MyScripts/mySystem.py >Traceback (most recent call last): > File "<string>", line 1, in <module> > File "/home/naveed/Desktop/gem5/src/python/m5/main.py", line 388, in >main > exec filecode in scope > File "configs/MyScripts/mySystem.py", line 26, in <module> > membus = CoherentXBar() >NameError: name 'CoherentXBar' is not defined > >Can you please let me know why I am having this error? By the way, how you >figure out that they replaced the Bus() with CoherentXBar()? I mean, is >there any reference guide for this purpose? > >Thanks in advance > > >> Hi Naveed, >> >> The Bus is renamed Xbar, and you need to specify either a coherent or >>non >> coherent one. In your case: >> >> membus = CoherentXBar() >> >> ...should do the trick. >> >> Concerning the power and clock domains, I suggest having a look at >> configs/examples/se.py and fs.py to see how it is done. If you do not >> want >> to use the DVFS functionality you can create a single system power and >> clock domain. >> >> Andreas >> >> On 30/09/2014 16:54, "Naveed Ul Mustafa via gem5-users" >> <gem5-users@gem5.org> wrote: >> >>> >>>Hi All, >>> >>>I am a new user of gem5. I am following the slides available on >>> following >>>link. >>> >>>I am running following configuration script. Lines whic prodcue error >>> are >>>marked by comments >>>-------------------------------------------------------- >>>import m5 >>>from m5.objects import * >>> >>>MyCache=BaseCache(assoc=2, mshrs = 10, tgts_per_mshr=5, hit_latency=1, >>>response_latency=2) >>> >>>MyL1Cache=MyCache(is_top_level= True) >>> >>> >>>mycpu = TimingSimpleCPU(cpu_id=0) >>> >>>mycpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), >>> MyL1Cache(size = '256kB'), >>> MyCache(size = '2MB', hit_latency=2, >>>response_latency=4) >>> ) >>> >>>mysystem = System(cpu=mycpu, >>> cache_line_size = '64', >>> physmem = SimpleMemory(), >>> membus = Bus()# İt says in error that System has no attribute >>>"membus" >>> ) >>># create the interrupt controller >>>mycpu.createInterruptController() >>>mycpu.connectAllPorts(system.membus)# Again same error message that is >>>System has no attribute "membus" >>>mycpu.clock= '2GHz'#Error message: TimingSimple CPU has no attribute >>>"clock" >>> >>>root = Root(full_system=False,system = mysystem) >>>root.system.cpu.workload=LiveProcess(cmd= 'hello', executable >>>='/home/naveed/Desktop/gem5/tests/test-progs/hello/bin/arm/linux') >>> >>># instantiate configuration >>>m5.instantiate(root)#Error in unproxying param 'clk_domain' of system >>> >>>exit_event = m5.simulate() >>>print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() >>> >>>---------------------------------------------------------------------Wil >>>l >>>be thankful for any help >>> >>>Naveed Ul Mustafa >>> >>>_______________________________________________ >>>gem5-users mailing list >>>gem5-users@gem5.org >>>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy >>the >> information in any medium. Thank you. >> >> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, >> Registered in England & Wales, Company No: 2557590 >> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 >>9NJ, >> Registered in England & Wales, Company No: 2548782 >> > > >Naveed Ul Mustafa > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. 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