Hello everyone! I want to "just" separate read latency and write latency of tag (in L1 and in the case that tag is written). Do you know which file( or files) should be changed? I suppose I should change "Tags.py", "base.hh", "base.cc" files in <path_to_gem5>/src/mem/cache/tags to add a write latency parameter for tag and maybe in the cache_impl.hh. but I'm not sure. I'd be thankful if someone helps me with my question. thanks in advance.
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
