Are you running in SE or FS mode? For 32-bit ARM code registers 16->32 are various shadow copies of registers for different interrupt/exception levels.
Ali On 10/29/14, 10:56 AM, "Negar Miralaei via gem5-users" <[email protected]> wrote: >Hi guys, > >I'm looking at integer register values/accesses at the Physical Register >File. Running few applications (from Spec2006), it shows no accesses for >reg#13 to reg#42 (in some cases the range is from reg#15 to reg#33). I >was wondering whether anyone knows if these registers are reserved for >specific conditions or interrupts, which would be used at FS mode. >I'm using ARM platform, and running in the SE mode. > >Thanks, >Negar > >-- >Negar Miralaei >http://www.cl.cam.ac.uk/~nm537/ >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
