Hi Azadeh,
It should not be too difficult. Besides adding '—caches' command line, here is
all you have to do to trace the d-side. Note that the trace is in a binary
format (and not ASCII).
Andreas
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -52,6 +52,7 @@
from ExeTracer import ExeTracer
from MemObject import MemObject
from ClockDomain import *
+from CommMonitor import CommMonitor
default_tracer = ExeTracer()
@@ -267,7 +268,9 @@
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
- self.dcache_port = dc.cpu_side
+ self.dmon = CommMonitor(trace_enable=True)
+ self.dcache_port = self.dmon.slave
+ self.dmon.master = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if iwc and dwc:
From: Azadeh Shirvanian via gem5-users
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Reply-To: Azadeh Shirvanian
<azadeh.shirvan...@gmail.com<mailto:azadeh.shirvan...@gmail.com>>, gem5 users
mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Sunday, 18 January 2015 14:46
To: "gem5-users@gem5.org<mailto:gem5-users@gem5.org>"
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: [gem5-users] Communication monitor is not connected on both sides
Dear all
I need to trace the address and the data exchanged between CPU and L1 data
cache - in SE mode on X86, classical memory - and I have modified the
CacheConfig.py to add CommMonitor in the following way:
After the line about setting the cache line size (system.cache_line_size =
options.cacheline_size) I have added these two lines:
system.icachemonitor = CommMonitor(trace_file='Icachecontent.ptrc')
system.dcachemonitor =
CommMonitor(trace_file='DCache_content.ptrc',trace_enable=True)
Then after:
if buildEnv['TARGET_ISA'] == 'x86':
I have commented this line:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache())
and instead, inserted these three lines:
system.dcachemonitor.master = dcache.cpu_side
system.icachemonitor.master = icache.cpu_side
system.cpu[i].addPrivateSplitL1Caches(system.icachemonitor.slave,
system.dcachemonitor.slave,
PageTableWalkerCache(),
PageTableWalkerCache())
Then I have compiled using:
scons build/X86/gem5.opt
And then run:
build/X86/gem5.opt configs/example/se.py -c
tests/test-progs/hello/bin/x86/linux/hello
As a result, I get in CacheConfig.py a:
SyntaxWarning: Import * only allowed at module level
def config_cache(options, system) :
fatal: Communication monitor is not connected on both sides
@ tick 0
[init:build/X86/mem/comm_monitor.cc, line 144]
Memory Usage: 627592 KBytes
Program aborted at tick 0
Aborted (core dumped)
Then I saw in email threads that some people have modified BaseCPU.py, so
keeping the changes in CacheConfig.py, I tried that as well. In the following
section in BaseCPU.py:
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
I commented the following line:
self.dcache_port = dc.cpu_side
and added these lines instead:
self.L1MONITOR = CommMonitor(trace_file="L1.txt")
self.dcache_port = self.L1MONITOR.slave
self.L1MONITOR.master = dc.cpu_side
After compiling and running in the same way as above, I do not get the warning
message anymore, but the fatal error still exists:
fatal: Communication monitor is not connected on both sides
@ tick 0
[init:build/X86/mem/comm_monitor.cc, line 144]
Memory Usage: 627564 KBytes
Program aborted at tick 0
Aborted (core dumped)
Actually, it is not clear to me which file I should modify: BaseCPU.py or
CacheConfig.py or both. And I would really like to know how I can get rid of
this fatal error and finally see the trace.
I would appreciate any help.
Azadeh
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered
in England & Wales, Company No: 2557590
ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
Registered in England & Wales, Company No: 2548782
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
