Hello Users, I have a basic read-after-write and write-after-read dependency question. If DRAM controller receives a write request, then it is added to the write queue and its response is sent immediately. When its response is being sent, access(pkt) method from AbstractMemory is called which actually writes the data. If a read request to the same address was pending in the readQueue (note that this read request arrived at DRAM controller before the write), then this request would read new data written. Wouldn't this violate WAR dependency? (I am sure WAR is handled properly, otherwise benchmarks would have resulted in incorrect output, but I don't seem to be able to figure out where the dependencies are handled in memory system).
Thank you, -Rizwana
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