Hi In the ARM FS simulation which cache coherence model is used. When I look at the build_opts/ARM, then I can see Protocol as MI_example. If that is the one used then how come 2 level cache hierarchy is implemented (because the MI example has 1 level cache hierarchy)?
And ARM uses Classic Memory Model instead of Ruby. If yes, then doesn't it then implements MOESI protocol. if no, then is Ruby supported? -- Have a great day! Thanks and Warm Regards Davesh Shingari Master's in Computer Engineering [EE] Arizona State University [email protected] ᐧ
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