[gem5-users] why miss latency cycles for ICache is greater than number of cpu cycles simulated

[Naveed Ul Mustafa]

Hi all,

I want to calculate the portion of total execution time when processor is
waiting for cache.

1) Does the stat file has any such parameter which gives portion of the
total execution time when processor waited for cache response?

2) In mys stat file there are two numbers as listed below.

system.cpu.numCycles                        145115952                     
 # number of cpu cycles simulated

and

system.cpu.icache.overall_miss_latency::total   6949036942                
      # number of overall miss cycles

How is it possible that number of total miss cycles for Icache is greater
than number of cpu cycles simulated??

Or I misunderstand the numbers?

Please guide me.

Thanks

Naveed Ul Mustafa

_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users