Hello Users, I am simulating ARM detailed(O3) quad core CPU with private L1 cache and shared L2 cache. I am trying to regulate the number of outstanding requests a core can generate. I know that by statically changing the number of number of L1 MSHRs(passed as parameters from O3v7a.py), i can restrict the number of outstanding requests of a core.
I would like to have private cache with different number of L1 MSHRs for each core(for eg: core0 - 1MSHR, Core2 - 3MSHRs ..etc). How to make this assignment through configuration file? Also i would like to dynamically change this allocation. Can i make use of m5(special instruction) to do this? Can anyone shed some light on this. Thanks, Prathap
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