Hi fernando, I figured that out. It seems like the address is for the ram. Do you know how can I get the address for the cache(l1i, l1d and L2) being used. Thanks in advance!
*Regards,* *Kassan Unda* *Doctoral Candidate* *Computer Engineering* *Missouri S&T (Formerly University of Missouri Rolla)* *WebPage: http://web.mst.edu/~kutx9 <http://web.mst.edu/~kutx9>* *"Do not go where the path may lead, go instead where there is no path and leave a trail."* Ralph Waldo Emerson On Tue, Jun 2, 2015 at 2:03 AM, Fernando Endo <[email protected]> wrote: > Hello, > > I'm not familiar with the instruction trace shown, but I'm my opinion, 'D' > is for data and 'A' for address. It seems that they represent a common bus > relying all execution units, then 'D' always have in the traces the last > result processed. Again, this is a hypothesis. > > A memory access in the Atomic CPU model is answered immediately. > Furthermore, you have to check if the addresses are physical or logical. > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > > > 2015-06-01 23:38 GMT+02:00 kassan unda <[email protected]>: > >> Hello all, >> I generated the instruction traces using >> **./build/X86/gem5.debug --debug-flags=Exec --debug-file=trace >> ./configs/example/se.py --sys-clock=2GHz --cpu-type= >> atomic >> --caches --l2cache --l2_size=1MB --l1d_size=64kB --l1i_size=32kB -c >> ./tests/test-progs/hello/bin/x86/linux/hello >> >> >> 1000: system.cpu T0 : @_start+6.0 : POP_R : ld t1, SS:[rsp] : >> MemRead : D=0x0000000000000001 A=0x7fffffffee20 >> 1500: system.cpu T0 : @_start+6.1 : POP_R : addi rsp, rsp, 0x8 : >> IntAlu : D=0x00007fffffffee28 >> 2000: system.cpu T0 : @_start+6.2 : POP_R : mov rsi, rsi, t1 : >> IntAlu : D=0x0000000000000001 >> 3000: system.cpu T0 : @_start+7.0 : MOV_R_R : mov rdx, rdx, rsp : >> IntAlu : D=0x00007fffffffee28 >> 3500: system.cpu T0 : @_start+10.0 : AND_R_I : limm t1, >> 0xfffffffffffffff0 : IntAlu : D=0xfffffffffffffff0 >> >> *This is what the trace looks like. I am trying to make sense out of >> this. at 1000 ticks or 3rd cycle there is a memory read* >> >> POP_R : ld t1, SS:[rsp] : MemRead : D=0x0000000000000001 >> A=0x7fffffffee20 >> I am trying to understand which level of cache is being used and the >> loaction in the cache being used. Do these addresses represent that? >> D=0x0000000000000001 A=0x7fffffffee20 also what D represents ans what A >> represents? >> If these addresses do not represent the address of memory being used then >> how can I get that info. >> Thanks in Advance! >> >> >> *Regards,* >> *Kassan Unda* >> >> *Doctoral Candidate* >> *Computer Engineering* >> *Missouri S&T (Formerly University of Missouri Rolla)* >> *WebPage: http://web.mst.edu/~kutx9 <http://web.mst.edu/~kutx9>* >> >> *"Do not go where the path may lead, go instead where there is no path >> and leave a trail."* Ralph Waldo Emerson >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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