Hi Prathap, The DRAM controller in gem5 is flexible enough to support die-stacked memories, all you need is to specify suitable timing and architecture parameters. You already find a WideIO model, as well as an HMC vault model. You should be able to add WideIO2 and HBM without much effort (just subclass DRAMCtrl and set the appropriate parameters).
Andreas From: gem5-users <gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>> on behalf of Prathap Kolakkampadath <kvprat...@gmail.com<mailto:kvprat...@gmail.com>> Reply-To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Thursday, 18 June 2015 21:57 To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: [gem5-users] How to model a die-stacked DRAM? Hello Users, Has anyone tried to model a die-stacked DRAM using gem5's classic memory system? I read a couple of papers, in which they model die-stacked DRAM using DRAMSim2. How difficult it would be to model and any pointers on where to start? Thanks, Prathap Kumar Valsan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782
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