Hello, It seems that you're running a FS simulation, that's why those event messages appear. Skid buffer are intended to temporary hold instructions comming from an earlier pipe stage when a pipe stall happens. Nevertheless, it is strage for me that increasing the issue width alone produces overflows. Then, for the fetch width you may check the decode skid buffer code, and for the decode width, check the rename skid buffer.
Note: I used to set the same fetch, decode, rename, dispatch widths. Now with a fetch buffer, it makes sense to increase the fetch width. Regards, -- Fernando A. Endo, PhD student and researcher Université de Grenoble, UJF France 2015-08-21 7:55 GMT+02:00 Davesh Shingari <[email protected]>: > Hi > > I a running SPEC benchmarks in detailed mode with X86 architecture. The > simulations runs fine, but when I change either fetch width or issue width > or decode width, then the simulation crashes with following assertion > failure: > > Switch at curTick count:10000 > info: Entering event queue @ 10289011536500. Starting simulation... > Switched CPUS @ tick 10289011546500 > switching cpus > info: Entering event queue @ 10289011546500. Starting simulation... > **** REAL SIMULATION **** > info: Entering event queue @ 10289011547000. Starting simulation... > *gem5.opt: build/X86/cpu/o3/decode_impl.hh:409: void > DefaultDecode<Impl>::skidInsert(ThreadID) [with Impl = O3CPUImpl, ThreadID > = short int]: Assertion `skidBuffer[tid].size() <= skidBufferMax' failed.* > Program aborted at cycle 10289012648000 > > And I am also not clear why I am getting 3 lines with Entering event queue > with different cycle value. > > -- > Have a great day! > > Thanks and Warm Regards > Davesh Shingari > Master's in Computer Engineering [EE] > Arizona State University > > [email protected] > ᐧ > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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