Anmol Mohanty via gem5-users <gem5-users <at> gem5.org> writes:
> > > > Hi gem5ites, > > I am facing this pesky error repeatedly. Last time, to resolve it, I rebuilt gem5 and it did not reappear, but this time it seems to be persisting. I want to get to the root of the issue and clear it for good. > > The error is:- > > gem5.opt: build/ARM/cpu/simple/atomic.cc:359: virtual Fault AtomicSimpleCPU::readMem(Addr, uint8_t*, unsigned int, unsigned int): Assertion `!pkt.isError()' failed. > > > I am trying to do a simple bootup of Android on gem5 configured as an ARM processor. > > The above error comes in most of CPU types. > > If I use timing CPU however, I get a slightly different error > > gem5.opt: build/ARM/mem/coherent_xbar.cc:251: bool CoherentXBar::recvTimingReq(PacketPtr, PortID): Assertion `routeTo.find(pkt->req) == routeTo.end()' failed. > > > If someone has experienced this and has troubleshooted this, comments would be welcome. > > Thanks, > Anmol Mohanty > > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users Hi, Did anybody fix this issue. I am also facing the same. I am trying the full system simulation using TimingSimpleCPU. ./build/ARM/gem5.opt configs/example/fs.py --cpu-type TimingSimpleCPU I am getting a compilation error. Somebody please suggest how can I fix this. **** REAL SIMULATION **** warn: Existing EnergyCtrl, but no enabled DVFSHandler found. info: Entering event queue @ 0. Starting simulation... gem5.opt: build/ARM/mem/coherent_xbar.cc:251: bool CoherentXBar::recvTimingReq(PacketPtr, PortID): Assertion `routeTo.find(pkt- >req) == routeTo.end()' failed. Program aborted at cycle 30154500 Aborted (core dumped) _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
