Hi, Thank you for your fine grained tests, I will change my configuration right now.
Best regards. On 01/11/2015 20:37, Prathap Kolakkampadath wrote: > Hello Pierre/Fernando, > > > Thanks for your replies. > Based on [1] the ROB entries for cortex-A15 is 60. However, as per this > article > http://www.anandtech.com/show/6787/nvidia-tegra-4-architecture-deep-dive-plus-tegra-4i-phoenix-hands-on/2, > the > number of ROB entries are 128. I did run some tests changing the ROB size > to 128 and proportionally increasing the size of LSQ and IQ((3 times the > defaults values of gem5 O3V7a). > Now the results look similar to the real platform. So i am not sure how far > the cortex-A15 settings mentioned in [1] is correct. > > Thanks, > Prathap > > > On Sun, Nov 1, 2015 at 5:49 AM, Fernando Endo <fernando.en...@gmail.com> > wrote: > >> Hello, >> >> Regarding [1], the instruction latencies of a A15 can be set as those of >> the A9 in [2], or as those of an A72 ( >> http://infocenter.arm.com/help/topic/com.arm.doc.uan0016a/cortex_a72_software_optimization_guide_external.pdf >> ) >> >> Best regards, >> >> -- >> Fernando A. Endo, Post-doc >> >> INRIA Rennes-Bretagne Atlantique >> France >> >> >> 2015-10-20 9:36 GMT+02:00 Pierre-Yves Péneau <pierre-yves.pen...@lirmm.fr> >> : >> >>> Hi, >>> >>> You can find some informations on [1] for Cortex A7 and A15. See [2] for >>> Cortex A8 and A9. >>> >>> [1] http://damien.courousse.fr/pdf/2015-Endo-HiPEAC-RAPIDO.pdf >>> [2] http://damien.courousse.fr/pdf/Endo2014-gem5-SAMOS.pdf >>> >>> >>> On 19/10/2015 17:17, Prathap Kolakkampadath wrote: >>>> Hello Users, >>>> >>>> What is the exact configuration for cortex A15? >>>> The configuration file "configs/common/O3_ARM_v7a.py" doesn't seems to >>>> replicate cortex A15 correctly. For example based on the below document, >>>> cortex A15 should have ROB of size 128, which 3 times more than the >>> size of >>>> ROB(40) specified in the gem5 configuration file. >>>> How to find the exact information regarding ROB/LQ/SQ etc..? >>>> >>>> >>> http://www.anandtech.com/show/6787/nvidia-tegra-4-architecture-deep-dive-plus-tegra-4i-phoenix-hands-on/2 >>>> >>>> Thanks, >>>> Prathap >>>> >>>> >>>> >>>> _______________________________________________ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> -- >>> +----------------------------------------------------------+ >>> | Pierre-Yves Péneau | first.last at lirmm.fr | >>> | PhD student - LIRMM - Sysmic | + 33 4 67 41 85 85 | >>> | Bâtiment 4 Bureau H2.2 | http://walafc0.org | >>> +----------------------------------------------------------+ >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- +----------------------------------------------------------+ | Pierre-Yves Péneau | first.last at lirmm.fr | | PhD student - LIRMM - Sysmic | + 33 4 67 41 85 85 | | Bâtiment 4 Bureau H2.2 | http://walafc0.org | +----------------------------------------------------------+
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