Hello, Im my opinion, you have only to change the code in src/arch/arm/, except if you want to create a new opClass.
Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2015-12-11 5:24 GMT+01:00 Hemendra Rawat <[email protected]>: > Hi All, > > I want to add few custom instructions in ARM NEON instruction set. My > custom instructions will work on two 128 bit source registers and > produce one 128 bit destination register, similar to VADD instruction > in NEON. I'm > interested in measuring performance improvements with new custom > instructions. I'm planning to integrate new instructions in the same > way as VADD instruction is added in GEM5. > > According to my present understanding of GEM5 and ARM ISA > > 1) In ARM v7 reference manual, the encoding for VADD instruction is : > A = 1000 , B = 0, U = 0, C = - > > 2) The GEM5 implementation is done as follows: > > - The instruction is defined as a class in > gem5-stable/src/arch/arm/isa/insts/neon.isa > > vaddCode = ''' destElem = srcElem1 + srcElem2; ''' > > threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", > unsignedTypes, 2, vaddCode) > > and then added to a dictionary. > > > - Then the opcodes and encoding for the instruction is done > in gem5-stable/src/arch/arm/isa/formats/fp.isa > > > static StaticInstPtr > decodeNeonThreeRegistersSameLength(ExtMachInst machInst) > { > const bool u = THUMB ? bits(machInst, 28) : > bits(machInst, 24); > const uint32_t a = bits(machInst, 11, 8); > const bool b = bits(machInst, 4); > const uint32_t c = bits(machInst, 21, 20); > case 0x8: > if (b) { > …... > if (u) { > return > decodeNeonUThreeReg<NVsubD, NVsubQ>(q, size, machInst, vd, vn, vm); > } else { > return > decodeNeonUThreeReg<NVaddD, NVaddQ>(q, size, machInst, vd, vn, vm); > } > } > > - During GEM5 build the ISA parser reads these files and > automatically creates the proper instruction definitions in > build/ARM/arch/arm/generated/decoder-ns.cc.inc > > So, If i want to add new NEON instructions, I just need to find unused > opcodes like ( A = 1000 , B = 0, U = 0, C = 1) and then make changes > in neon.isa and fp.isa, the rest is taken care by > GEM5 and ISA parser ? > > I would really appreciate, if someone can tell me thay my > understanding is right or I need to make some other changes in GEM5 as > well to add custom instructions. > > > Thanks > Hemendra Kumar Rawat > Graduate Student > Department of Electrical & Computer Engineering > Virginia Tech > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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