Andreas Hansson <Andreas.Hansson <at> arm.com> writes:

> 
> 
> Hi Prathap,
> 
> We have some patches to restrict way allocation in the cache itself (not 
per core though). You can probably use that as a starting point. I’m afraid 
beyond that you will need to add the appropriate functionality to look at 
e.g. masterId and decide on a
>  way. I’ll try and get those patches posted in the next few days.
> 
> Andreas
> 
> 
> 
> From: Prathap Kolakkampadath <kvprathap <at> gmail.com>Reply-To: gem5 
users mailing list <gem5-users <at> gem5.org>Date: Monday, 8 June 2015 
17:29To: gem5 users mailing list <gem5-users <at> gem5.org>Subject: [gem5-
users] L2 cache partitioning
> 
> 
> 
> Dear Users,
> 
> I am using ARM Full System configuration, where L2 is 8-way set 
associative shared Last Level Cache. I am trying to partition the L2 cache 
by
> ways among four cores, so that each core gets two ways. 
> 
> Is there a hardware support(configuration register) available to do this? 
If not can anyone throw some pointers to achieve way partitioning.
> 
> Thanks in advance.
> 
> Prathap
> 
> 
> 
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Hi Andreas,

I am also looking for the same feature in gem5. I was wondering if you have 
posted your patches. If you did, can you please give me a pointer to them?

Thanks,
Farzad
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