I don't think there is an existed approach. Just a remind that store and load behaves different according to the pipeline stages. Store is non-speculative. At the head of ROB, the store can be committed but the real memory access happens when the store comes to the head of the store buffer.
On Thu, Apr 7, 2016 at 1:02 AM, Vignesh Radhakrishnan <[email protected] > wrote: > Hi, > > I would like to perform certain operations on an O3 CPU when a last level > cache miss happens. I need to detect this when the instruction causing the > cache miss, reaches the head of ROB. > > So what i thought of doing was: > > In cache_impl.hh, we have the bool satisfied in recvTimingResp() routine, > that tells us if the miss had happened as it happens to be the return value > of the access() routine. > I can retreieve the PC causing that sent the packet using : > > - pkt->req.getPC(). > > > I was planning to include a global variable that stores whether a miss has > occured and the PC along with it. > > In the commit_impl.hh, when the instruction reaches the head, i check if > the instruction is a load or a store and compare its PC with the miss > causing instruction. > > Is there any other approach that tells that is already present in Gem5 > structures, that can help me detect the miss and i can know the instruction > that caused it as well? > > Thanks and regards, > Vignesh Radhakrisnan > > > > -- > http://vigneshradhakrishnan.blogspot.com/ > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- yw
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
