Hi Marcos, It really comes down to a question of what you are trying to model. The gem5 cache hierarchy is by default mostly inclusive, so there is no need for this parameter to be set to True. However, if you want to make a level of the cache hierarchy mostly exclusive, you will most likely want to ensure that the caches above this level (closer to the master) write back clean lines.
Andreas On 03/05/2016, 04:34, "gem5-users on behalf of Marcos Horro Varela" <[email protected] on behalf of [email protected]> wrote: >Hello all, > >I was looking through the configuration of cache memories in the classic >model, and I found that in the configs/common/Caches.py, in the L1_DCACHE >class, the value writeback_clean is set to False. Nevertheless, in >src/mem/cache/Caches.py it is said that: "In general this (param) should >be set to True for anything but the last-level cache". Thus, is this >instantiaton coherent? Because in the CacheConfig.py it is NOT set to >True either. > >Thanks > >Best regards, > >-- >Marcos Horro Varela, >BSc student, University of A Coruña (UDC) >+34 618 62 67 37 >http://markos-horro.com >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
