Hi ,
I am using SE simulation mode, with X86 as my target. I dint change any of
parameters or the code of gem5. I am accessing each set of a cache and
measuring the delay to access it, using rdtsc instruction. Im getting some
delay pattern for the sets. Set 0 , set 16, set 32 like this getting more
delay and other sets are having less delay.
Sample Code:
.....
t0=rdtsc();
victim_array[ index ]=2;
t1=rdtsc();
printf("%ld" , (t1-t0));
.....
One of the reason of this measure(quantity) is the hit. lookup latency of
L1 and L2 and RAM . But still many other delays are contributing to this.
How can I know what other factors (with what amount) are contributing to
that total delay of accessing.?
Thank you
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