Hi,
I'm trying to implement a pseudo-instructions that executes a
read-modify-write type of operation. So, I'm getting the required data from
memory using SETranslatingPortProxy class. Then I modify the data I got and
write it back to the same address. However, I need that the time to write
the packet back to the memory to be computed, so instead of sending a
functional request to the memory system, I'm sending a timing request.
The problem occurs when I return from my pseudo-instruction to the main
program. Since I don't deal with the response packet that the memory system
sends to me, my simulation stops at
bool
SlavePort::sendTimingResp(PacketPtr pkt)
{
assert(pkt->isResponse());
return _masterPort->recvTimingResp(pkt);
}
because
gem5.opt: build/X86/mem/port.cc:252: bool
SlavePort::sendTimingResp(PacketPtr): Assertion `pkt->isResponse()'
failed.
So my question is: how do I capture the response packet that is sent?
Or is there a better way to compute the time riquered to write the
data to the main memory?
I really hope any of you could help me.
Thanks in advice.
--
*Geraldo Francisco de Oliveira Junior*
Mestrando em Computação - Universidade Federal do Rio Grande do Sul
Bacharel em Ciência da Computação - Universidade Federal de Viçosa
BSMP Computer Engineering - Portland State University
Técnico em Informática - Universidade Federal de Viçosa
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users