I am using arm_detailed. I'll check the pld instruction once I'm home and I'll write back. Thanks!
Felipe de Azevedo Piovezan On Jun 7, 2016 11:43, "Sam Ainsworth" <[email protected]> wrote: > Hmm, which CPU model? I know they work with arm_detailed, but I've not > tried with any of the others. Does a pld instruction change the sim_insts > number? > > Thanks, > > Sam > > > > On 2016-06-07 15:26, Felipe de Azevedo Piovezan wrote: > > Hello Sam, > Thanks for the fast reply :) > > I'm running on syscall emulation mode, so I believe (2) shouldn't be an > issue. > Here's the problem though. > > Let fe_mul() be a function consisting of a single basic block of about 400 > instructions, that is, no branches, no jumps, only sequential execution. > When I simulate this with some other code, I get the following stats: > > sim_insts 1572969 > > Now, I edit the assembly of the code to insert a single "pli" instruction > right at the start of fe_mul(): > > 00031620 <fe_mul>: > 31620: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} > 31624: e24dd0b0 sub sp, sp, #176 ; 0xb0 > 31628: e58d0024 str r0, [sp, #36] ; 0x24 > 3162c: f45ff014 pli [pc, #-20] ; 31620 <fe_mul> > > Notice the "pli" instruction at the 5th line. > > What should we expect here? This prefetch is pretty much useless, but if > this function fe_mul() is called about 1400 times, then we would like to > see an increase in the number of executed instructions. Instead, gem5 > reports: > > sim_insts 1572969 > > Exactly the same number! I've looked into the assembly, and the two > versions of this function differ by exactly one instruction, the "pli" one. > The compiler is not doing any tricks here. > I've done some tests inserting this instruction into different positions > of the code and the same result applies, but if I insert a harmless > instruction such as "add r0 r0 #0" then I get the expected result. > > > I will try running with a newer version of gem5. > > On 7 June 2016 at 11:22, Sam Ainsworth <[email protected]> wrote: > >> Hi Felipe, >> >> Gem5 can simulate these, with a few caveats: >> >> i) I think pli might be misinterpreted as a prefetch into the dcache (not >> positive on this though) >> >> ii) If you are in FS mode, gem5 will throw away any prefetches that miss >> in the 64 entry TLB (SE mode doesn't simulate the TLB properly). To get >> around this, you need to remove the lines referring to >> "state.req->isPrefetch()" in src/arm/arch/tlb.cc >> >> >> >> Thanks, >> >> Sam >> >> >> >> On 2016-06-07 14:42, Felipe de Azevedo Piovezan wrote: >> >> Hi all, >> >> Does anybody know whether gem5 is able to simulate the ARM instructions >> pli/pld (prefetch)? >> Looking at the source code, they seem to be simulated as no-ops. >> >> Thanks! >> -- >> Felipe >> >> _______________________________________________ >> gem5-users mailing >> [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > -- > Felipe > > _______________________________________________ > gem5-users mailing > [email protected]http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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