Hi Everyone, I am working on the stride prefetcher and tagged prefetcher in gem5 (gem5-stable-629fe6e6c781, the stable version last year). My benchmarks are spec2006 and the configuration of prefetcher is:
L1dcache-stride prefetcher degree=2 L1dcache-tagged prefetcher degree=2 L2 tagged prefetcher degree=2 No L1 icache prefetcher I use SE mode and start the benchmarks from a checkpoint with 40 Billion instructions, then warmup 1B and run 1B instructions. When I am doing the experiments, I found that sometimes icache issues a ReadReq which has the SAME cache block address as a earlier HardPFreq from L1dcache's prefetcher. This phenomenon confused me so much because as we all know the code's address range is different from the data's one. Considering gem5's prefetcher doesn't fetch the addresses across the page bound, such address conflict looks very weird. The code page should be far away from the data page, right? In addition, it seems that no TLB is available in SE mode. So the memory access addr should be physical address, right? (like pkt->getAddr()) Thanks in advance. gjins
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