Hi, Consider an alternate memory mapping, for example, every memory address X is supposed to be f(X), where f is some one-one mapping.
Lets say I want to observe the impact that this mapping has on cache performance, can I do this without modifying the static binary in gem5 ARM SE mode? I simply implemented such a mapping to transform each packet’s address before it accesses the I/D cache. This promptly leads me to a page fault. For the topology, I’ve placed my custom address mapping unit between the i(d)cache_port and the cpu_side of i(d) cache in src/cpu/BaseCPU.py. I wonder if it is absolutely necessary for me to generate a new static executable that has these transformed addresses built-in, or can I hack my way around in gem5 ARM SE? Also, how are the globals/constants of the binary stored/accessed by gem5? Any comments/pointers/references would be appreciated :) Best, Seshan _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
