Hello,
I'm trying to implement a trace cache for O3 cpu in gem5. Could anyone please provide pointers to prior implementations and/or discussion threads that can help me get started? Thank you! Thanks, Gokul Subramanian Ravi, Graduate Student, ECE Dept., University of Wisconsin-Madison ________________________________ From: gem5-users <[email protected]> on behalf of [email protected] <[email protected]> Sent: Saturday, December 31, 2016 11:00 AM To: [email protected] Subject: gem5-users Digest, Vol 125, Issue 24 Send gem5-users mailing list submissions to [email protected] To subscribe or unsubscribe via the World Wide Web, visit http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users or, via email, send a message with subject or body 'help' to [email protected] You can reach the person managing the list at [email protected] When replying, please edit your Subject line so it is more specific than "Re: Contents of gem5-users digest..." Today's Topics: 1. Re: When will gem5v become available in gem5 mainline? (Chao Yan) 2. Thread binding to cores in FS mode simulation of ALPHA ISA (Zamshed Chowdhury) ---------------------------------------------------------------------- Message: 1 Date: Fri, 30 Dec 2016 13:16:51 -0600 From: Chao Yan <[email protected]> To: [email protected] Subject: Re: [gem5-users] When will gem5v become available in gem5 mainline? Message-ID: <CALxA4=CFvk7QeLiaT=3fhzgvbp5ws_dwgmn2hkpfpuwb+yc...@mail.gmail.com> Content-Type: text/plain; charset="utf-8" Hello, I would like to simulate hypervisors using gem5. The most recent proposal is *Seyed Hossein Nikounia ยท Siamak Mohammadi, "Gem5v: a modified gem5 for simulating virtualized systems", the journal of supercomputing, April 2015. * Could anyone please provide information about when gem5v would become a part of gem5 mainline? Thanks for helping in advance. Cheers, Chao -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20161230/e09d8989/attachment-0001.html> ------------------------------ Message: 2 Date: Fri, 30 Dec 2016 19:29:57 -0600 From: Zamshed Chowdhury <[email protected]> To: gem5 users mailing list <[email protected]> Subject: [gem5-users] Thread binding to cores in FS mode simulation of ALPHA ISA Message-ID: <cacs3f68ko+as6deetdtaqrogxdzptppxr_mseaeofwckgmc...@mail.gmail.com> Content-Type: text/plain; charset="utf-8" Hi, I am trying to simulate ALPHA in FS mode (with 4 cores and 8 cores, OoO cpu) to run SPLASH2 and PARSEC benchamrks. The applications run fine, however whenever I am checking the *numCycles *value of the CPUs in the Stats.txt file, I can see that not all the cpus are active at all times. Especially inside a pthread_barrier_wait() statement. Also, for 8 cores and 7 threads, I am getting 5 active cores but the active cores change dynamically. I am trying to understand the activity pattern of the cores during a simulation by looking at the numCycles value of the cpus. Is there any way to bind the threads to particular cores, other than using pthread cpu affinity function? Best regards. -- Zamshed Iqbal Chowdhury Graduate Student Dept. of ECE UMN, TC -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20161230/ef18fd55/attachment-0001.html> ------------------------------ Subject: Digest Footer _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users gem5-users Info Page - m5 sim<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> m5sim.org Discussion for users of the gem5 simulator. To see the collection of prior postings to the list, visit the gem5-users Archives. (The current archive ... ------------------------------ End of gem5-users Digest, Vol 125, Issue 24 *******************************************
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