Hello, You can find the information on caches in m5out/config.ini under [system.cpu0.dcache], [system.cpu0.icache] etc. (search for "type=cache"). You may want to see src/mem/cache/Cache.py for Cache SimObject declaration, configs/common/Caches.py for base implementations of the caches (latency, associativity etc.). For more information check: http://learning.gem5.org/book/part1/cache_config.html
If you are looking for timing requirements of the memory, they are defined in src/mem/DRAMCtrl.py (also in the config.ini file: system.mem_ctrls) Latency can be found in m5out/config.ini file under system.realview.vram or system.realview.nvmem (type=SimpleMemory). SimpleMemory latency is defined in src/mem/SimpleMemory.py Hope these helps. Thanks and kind regards Serhat Gesoglu ________________________________________ From: gem5-users [gem5-users-boun...@gem5.org] on behalf of Moussa, Ayman [ayman.mouss...@imperial.ac.uk] Sent: 08 February 2017 19:02 To: gem5 users mailing list Subject: [gem5-users] Simulated data information - Cache and memory Hi everyone Could someone please tell me what parameters represent information about the cache? i.e l1,l2,l3 I and D cache sizes, associativity , access time etc. Is there any information about memory access time too? I searched the stats.txt and config.ini but I could not find it anything about cache sizes or memory access time. I'm using the se.py configuration script but did not supply any arguments (l1d_size etc) so what cache sizes does gem5 default to using if none are supplied? Thanks _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
