Hi all, I am trying to build a hierarchy of caches and tester CPUs using memtest (configs/examples/memtest.py) as my reference. I am able to connect regular XBars and caches normally, but I want an *N*-ported connection between a cache and a XBar (i.e. *N* simultaneous requests should be able to go from XBar to cache and vice versa). How do I achieve this? Also, I would like to know how to simulate multiple channels in the main memory.
Any pointers/explanation is highly appreciated. Thanks in advance for your help! Subhankar Pal | Computer Science & Engineering | University of Michigan, Ann Arbor
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