Hi all, Merely a thought: Could it be as simple as Ruby not really supporting coherent devices and interactions between cacheable and uncacheable address ranges?
ARM + classic definitely works well also for full system, but it would be good if you can verify that your particular (kernel, disk image etc) setup is working. Does anyone actually have any examples of Ruby being used for “complex” full system configurations? Thanks, Andreas From: gem5-users <gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>> on behalf of Jason Lowe-Power <ja...@lowepower.com<mailto:ja...@lowepower.com>> Reply-To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Date: Monday, 27 February 2017 at 15:22 To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Linux booting problem in ARM NOC Hi Sharjeel, It's clear that Ruby+ARM currently doesn't work. It's going to take some effort and some code changes in Ruby to get it to work correctly. It's good that a single core boots. You should try something *very simple* with 2 cores. For instance, use MI_example and the Pt2Pt topology with the simple network model. From here you'll be able to track down the problems easier. Once you have that working, you can slowly introduce other code and solve the problems that come with that. Jason On Mon, Feb 27, 2017 at 1:42 AM SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com<mailto:sharjeelsaeedkhi...@gmail.com>> wrote: Hi, I can boot linux on following to a point indicated. I can boot the same kernel on single core CrossbarGarnet. There is some issue with multi core in ARM NOC in full system. Any suggestions please, ./build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image /home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_2cpu.dtb --num-cpus=2 --cpu-type=timing --ruby --num-dirs=1 --garnet-network flexible --topology Torus --mesh-rows 2 Booting Linux on physical CPU 0x0 Initializing cgroup subsys cpuset Linux version 4.3.3 (bes...@jaguar.lirmm.fr<mailto:bes...@jaguar.lirmm.fr>) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0) ) #1 SMP PREEMPT Sat Jan 30 23:15:48 CET 2016 CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache Machine model: V2P-CA15 Ignoring memory range 0x100000000 - 0x480000000 cma: Reserved 16 MiB at 0x9f000000 Memory policy: Data cache writealloc On node 0 totalpages: 131072 free_area_init_node: node 0, pgdat 806e4300, node_mem_map 9ebf2000 Normal zone: 1024 pages used for memmap Normal zone: 0 pages reserved Normal zone: 131072 pages, LIFO batch:31 PERCPU: Embedded 12 pages/cpu @9ebd3000 s19392 r8192 d21568 u49152 pcpu-alloc: s19392 r8192 d21568 u49152 alloc=12*4096 pcpu-alloc: [0] 0 [0] 1 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048 Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=512MB root=/dev/sda1 PID hash table entries: 2048 (order: 1, 8192 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 496044K/524288K available (5125K kernel code, 155K rwdata, 1476K rodata, 268K init, 136K bss, 11860K reserved, 16384K cma-reserved) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xfff00000 (3072 kB) vmalloc : 0xa0800000 - 0xff000000 (1512 MB) lowmem : 0x80000000 - 0xa0000000 ( 512 MB) modules : 0x7f000000 - 0x80000000 ( 16 MB) .text : 0x80008000 - 0x8067a8c8 (6603 kB) .init : 0x8067b000 - 0x806be000 ( 268 kB) .data : 0x806be000 - 0x806e4e40 ( 156 kB) .bss : 0x806e7000 - 0x807091fc ( 137 kB) SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Preemptible hierarchical RCU implementation. Build-time adjustment of leaf fanout to 32. RCU restricting CPUs from NR_CPUS=32 to nr_cpu_ids=2. RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2 NR_IRQS:16 nr_irqs:16 16 L2C: failed to init: -19 Architected cp15 timer(s) running at 25.16MHz (virt). clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x5cdd39714, max_idle_ns: 440795202620 ns sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 4398046511084ns Switching to timer-based delay loop, resolution 39ns Console: colour dummy device 80x30 Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) CPU: Testing write buffer coherency: ok /cpus/cpu@0 missing clock-frequency property /cpus/cpu@1 missing clock-frequency property CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x80008280 - 0x800082d8 CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 Brought up 2 CPUs SMP: Total of 2 processors activated (7995.39 BogoMIPS). CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations cpuidle: using governor ladder cpuidle: using governor menu hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0 hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0 hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0 hw-breakpoint: CPU 0 failed to disable vector catch hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 1 hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 1 hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 1 Serial: AMBA PL011 UART driver 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 23, base_baud = 0) is a PL011 rev3 console [ttyAMA0] enabled best regards, Sharjeel On 21 February 2017 at 20:32, Jason Lowe-Power <ja...@lowepower.com<mailto:ja...@lowepower.com>> wrote: Hi Sharjeel, I think you've found another case where ARM isn't supported in Ruby. I would *guess* this is a problem with some kind of atomic/memory ordering operation. I would try simplifying your simulated system and building up until you find the problem. For instance, start with 1 core and make sure Linux boots. Then, two cores, etc. You may also want to try simpler topologies (e.g., Pt2Pt or crossbar) and using only a single directory. This could also be a problem with the memory ranges. Ruby only supports a single range with no gaps. I don't know what the ARM systems use. Jason On Tue, Feb 21, 2017 at 3:54 AM SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com<mailto:sharjeelsaeedkhi...@gmail.com>> wrote: Hi, I am trying to boot linuxv4.4 on ARM NOC. The booting process gets stuck and same set of instruction is executed again and again. Following is the set of instructions. ./build/ARM/gem5.debug --debug-flags= Exec,ExecTicks configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image /home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 --cpu-type=timing --mem-size=512MB --ruby --num-dirs=2 --garnet-network flexible --topology Mesh --mesh-rows 2 --numa-high-bit=28 Following instructions are show in the terminal 370581084500: system.cpu0 T0 : @smp_call_function_many+592 : dmb #0 : IntAlu : 370581085500: system.cpu0 T0 : @smp_call_function_many+596 : tsts r3, #1 : IntAlu : D=0x0000000000000000 370581086500: system.cpu0 T0 : @smp_call_function_many+600 : bne : IntAlu : 370581087500: system.cpu0 T0 : @smp_call_function_many+588 : ldr r3, [r1, #12] : MemRead : D=0x0000000000000003 A=0x9eb4c Looks like a sort of deadlock. Any suggestions please, if anyone can give in this matter. best regards, sharjeel _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org<mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
