Hi, I want to connect my system with 16 bidirectional 64-bit (~ x128 unidirectional) interfaces to an HBM 2.0 package. However, I could find the x128 interface definition only for HBM gen1 and not gen2 in src/mem/DRAMCtrl.py. Would it be correct to emulate an x128 HBM gen2 interface using the values of *device_bus_width, device_rowbuffer_size, banks_per_rank* of the gen1 model with the latency parameters of the gen2 model?
Thank you in advance! Subhankar
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
