Hello all, I am trying to have a monitor between the CPU and L1 Cache and added the following lines to "src/cpu/BaseCPU.py" as suggested here: http://gem5.org/General_Memory_System#Traffic_analysis_and_memory_trace_capture
self.monitor = CommMonitor() self.monitor.trace = MemTraceProbe(trace_file="l1trace.trc.gz") self.dcache_port = self.monitor.slave self.monitor.master = dc.cpu_side #dc is l1 data cache # "from CommMonitor import *" is also added. When I try to start the simulation, gem5 gives an error: NameError: global name 'MemTraceProbe' is not defined All the required protoc libraries are installed: libprotobuf-dev, python-protobuf, protobuf-compiler, libgoogle-perftools-dev and running "protoc --version" gives "libprotoc 2.5.0". Also gem5 does not complain about protoc libraries at the beginning of a build and build/X86/configs/have_protobuf.hh has the line "#define HAVE_PROTOBUF 1". I searched for a solution in this mailing list but could not find a solution (or the solutions suggested did not work). Anyone has any idea what might be the problem? Thanks and kind regards. Serhat Gesoglu _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
